Sorry that this new update took so long.
Finally I have a fully working AND faster viterbi decoder.
To do that I had to abandon gr-trellis. After re-evulation of the code and project with my mentor we decided to start on a new OOT module for generic channel decoding.
Let me introduce gr-celec (Communications Engineering Lab Error Correction) and my own volk library volk_fec.
Right now the volk library contains kernels for complex branch metric calculations and Viterbi path metric calculations.
Gr-celec contains a block for branch metric calculations and a viterbi block (with metric calculations included). The Viterbi Block takes complex samples as input, along with some information about the encoder (Number of States, Packetlength, Startstate, Endstate and a vector containing all possible Outputs for every state). It works with non-recursive and rate 1/n decoders. These simplifications allowed me to use a Butterfly structure for the path metric calculations. This resulted in a better loop unrolling and SIMD register management. The SSE4.1 Kernel is now approx. 3x faster than the generic kernel
Next on my to-do lists are some cosmetic changes for gr-trellis/examples.
After that I can start working on the Log-Map Decoder. This will be done from scratch as well and put into the gr-celec.